Fault current managing branch for surge-less current interruption in dc system

ABSTRACT

A circuit breaker and fault current managing branch thereof for power transmission using Direct Current (DC) applications. A surge suppressor having DC bus terminal, transmission line terminal, and common terminal. An auxiliary branch comprises a pre-chargeable capacitor. The capacitor is charged by the DC bus before the circuit breaker is closed for operation and the capacitor is connected to be discharged to the transmission line when the circuit breaker is opened in operation, for suppressing the surge voltage across the circuit breaker. The auxiliary branch may comprise a charge sub-branch comprising a first controlled semiconductor switch for closing the charge sub-branch and charging the capacitor by the DC bus before the circuit breaker is closed. The auxiliary branch may comprise a discharge sub-branch comprising a second controlled semiconductor switch for closing the discharge sub-branch and discharging the capacitor to the transmission line when the circuit breaker is opened in operation.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a U.S. National Stage Application under 35 U.S.C. §371 of International Patent Application No. PCT/IB2016/054850, which wasfiled on Aug. 11, 2016, which claims priority to Portuguese PatentApplication No. 108782, which was filed on Aug. 11, 2015, and PortuguesePatent Application No. 108775, which was filed on Aug. 12, 2015, all ofwhich are hereby incorporated by reference in their respectiveentireties.

TECHNICAL FIELD

The present disclosure relates to a circuit breaker and fault currentmanaging branch thereof, for power transmission using Direct Current(DC) applications, in particular for meshed DC grids, multi-terminalHigh Voltage Direct Current (HVDC) grids or HVDC lines.

BACKGROUND ART

Nowadays, electricity transmission and distribution by mean of DirectCurrent (DC) is becoming more popular. In the low and medium voltagelevel most of the traction systems employ DC networks to energize thetrains. Additionally, the advantages and feasibility of DC distributiongrids have been pointed out by many studies. The formation of smartgrids can be more easier, since the intelligent power electronic devices(like power electronic based converters, fast communication basedmeasurement systems, . . . ) are employed by DC distribution grids. Inthe high voltage level, DC transmission system is known to be the bestchoice for integration of bulk amount of electricity energy to the ACgrid. Conventional current source converters (CSCs) are in operation inmany DC links all over the world. On the other hand, voltage sourceconverters (VSCs) offer many advantages like active and reactive powerindependent controllability and less cross section of the cable.Additionally, emerging multi-terminal DC grid is another motivation forthe application of voltage source converters.

In spite of significant benefits of DC systems, the DC sideshort-circuit fault clearing is very challenging. Due to the lowerinductance of DC transmission lines and cables and also contribution ofDC bus capacitors into the fault current, DC short-circuit currents canrise up severely. To protect the converter against high and sharpshort-circuit currents it is necessary to develop very fast faultcurrent interruption technologies.

In last decades, attempts include research on electromechanical,solid-state and hybrid DC circuit breaker structures. As any othertechnologies, each of the mentioned structures has advantages anddrawbacks. In recent years, high power semiconductor technology hasimproved significantly both in terms of current and blocking voltagerating for a single-chip device. These improvements and the expectationfor more advances in future are motivations for research on topologiesof fast solid-state circuit breakers. Furthermore, in the modern hybridDC circuit breakers structure, the main fault current interruptionaction is usually done by the help of a solid-state circuit breaker(SSCB) branch. Thus, any improvement in SSCB technology may also improvethe performance of hybrid circuit breaker topologies.

SSCB has been one of the research topics in high power electronics andDC grids area in recent years. A DC solid-state circuit breaker topologyhas been proposed in J.-g. Mu, L. Wang, and J. Hu, “Research on maincircuit topology for a novel DC solid-state circuit breaker,” inIndustrial Electronics and Applications (ICIEA), 2010 the 5th IEEEConference on, 2010, pp. 926-930. The proposed topology utilizesthyristors as the main interrupter and also in its auxiliary branches.In addition to complexity of the proposed circuit, the unidirectionaloperation of proposed SSCB can be mentioned as the main drawbacks ofthis topology. Z-source DC circuit breakers can also be considered asone of the structures of solid-state circuit breakers. These structuresare usually proposed for medium DC voltage level. The bidirectionalityof power flow in Z-source DC circuit breaker can be challenging.

One of the complexities in design of fast DC circuit breakers islimiting the overvoltage resulting from the release of stored energy inthe inductive elements of DC system like DC cables and smoothinginductors. A research on separation of energy absorption branch andovervoltage suppression branch has been conducted in J. Magnusson, R.Saers, L. Liljestrand, and G. Engdahl, “Separation of the EnergyAbsorption and Overvoltage Protection in Solid-State Breakers by the Useof Parallel Varistors,” Power Electronics, IEEE Transactions on, vol.29, pp. 2715-2722, 2014. A surgeless solid-state circuit breaker isdiscussed in K. Sano and M. Takasaki, “A Surgeless Solid-State DCCircuit Breaker for Voltage-Source-Converter-Based HVDC Systems,”Industry Applications, IEEE Transactions on, vol. 50, pp. 2690-2699,2014 and the authors propose an overvoltage limiting and energyabsorbing branch including diodes, resistors and none-linear surgearresters. Id. A solid-state circuit breaker topology employing passiveelements for overvoltage suppression has been proposed in S. Negari andD. Xu, “A new solid-state HVDC circuit breaker topology for offshorewind farms,” in Power Electronics for Distributed Generation Systems(PEDG), 2014 IEEE 5th International Symp. on, 2014, pp. 1-5. In additionto its unidirectional functionality, the proposed topology utilizescoupled inductors. In fact, implementation of mentioned inductors wouldbe challenging for HVDC applications. More recently, the application ofwide band semiconductor devices is also investigated.

Typically, fast solid-state DC circuit breakers consist of a number ofsemiconductor switches like IGBTs, IGCTs or power MOSFETs. Generally, toguarantee the bidirectionality of power flow, two unidirectionalswitches are connected to each other. FIG. 1 shows three possibleconnections for construction of bidirectional valves. In practice, theconnection showed in FIG. 1 part (a) is usually used since it needs onlyone driver for both of the switches.

Absence of a natural zero crossing point for the current is a source ofproblem for fast switching actions in DC applications. FIG. 2(a) showssimplified equivalent circuit for a DC transmission system, including acircuit breaker, an ideal DC source, a line represented by a simplemodel and a short-circuit fault. The short-circuit fault divides thetransmission line into two sections. After low impedance short-circuitfault happens in the DC line, the circuit breaker voltage can be givenby (1).

$\begin{matrix}{V_{BR} = {V_{D\; C} - {R_{line}^{1} \cdot i_{sc}} - {L_{line}^{1} \cdot \frac{{di}_{sc}}{dt}}}} & (1)\end{matrix}$

Since the derivative of current is negative in short-circuit currentinterruption process, (−L¹ _(line)·di_(sc)/dt) will be a positive valueand the breaker voltage will increase. Typically, the rate of rise of DCshort-circuit current is extremely high. Considering fast identificationand interruption of fault current (less than 2 ms), the switchingovervoltage can reach to more than 2 times of nominal value which can bedefinitely destructive for the breaking device and other components ofDC system.

Two main topologies are introduced for solid-state DC circuit breakersin literature [14]. As it is depicted in FIG. 2(b), one of thetopologies uses nonlinear resistors in parallel with the IGBTs tosuppress the overvoltage and absorb the released energy. FIG. 2(c) showsanother topology of SSCB which equipped with a set of freewheelingdiodes in series with nonlinear resistors. The nonlinear resistors areusually available as metal oxide varistors (MOV) like ZnO surgearresters. Despite their common use, MOVs are known as expensive deviceswhich also have the aging problems and even possibility of catastrophicfailures [15].

These facts are disclosed in order to illustrate the technical problemaddressed by the present disclosure.

The following references, should be considered herewith incorporated intheir entirety:

-   [1] J.-g. Mu, L. Wang, and J. Hu, “Research on main circuit topology    for a novel DC solid-state circuit breaker,” in Industrial    Electronics and Applications (ICIEA), 2010 the 5th IEEE Conference    on, 2010, pp. 926-930.-   [2] J. Magnusson, R. Saers, L. Liljestrand, and G. Engdahl,    “Separation of the Energy Absorption and Overvoltage Protection in    Solid-State Breakers by the Use of Parallel Varistors,” Power    Electronics, IEEE Transactions on, vol. 29, pp. 2715-2722, 2014.-   [3] K. Sano and M. Takasaki, “A Surgeless Solid-State DC Circuit    Breaker for Voltage-Source-Converter-Based HVDC Systems,” Industry    Applications, IEEE Transactions on, vol. 50, pp. 2690-2699, 2014.-   [4] S. Negari and D. Xu, “A new solid-state HVDC circuit breaker    topology for offshore wind farms,” in Power Electronics for    Distributed Generation Systems (PEDG), 2014 IEEE 5th International    Symp. on, 2014, pp. 1-5.

SUMMARY OF THE INVENTION

It is described a surge suppressor for a DC power transmission circuitbreaker having a DC bus terminal, a transmission line terminal, and acommon terminal, said suppressor comprising an auxiliary branchcomprising a pre-chargeable capacitor, wherein the auxiliary branch isarranged such that:

-   -   the capacitor is charged by the DC bus before the circuit        breaker is closed for operation; and the capacitor is connected        to be discharged to the transmission line when the circuit        breaker is opened in operation, for suppressing the surge        voltage across the circuit breaker.

In an embodiment, the auxiliary branch comprises a charge sub-branchconnected between the DC bus terminal and the common terminal, saidcharge sub-branch comprising a first controlled semiconductor switch forclosing the charge sub-branch and charging the capacitor by the DC busbefore the circuit breaker is closed.

In an embodiment, the surge suppressor is arranged such that the firstcontrolled semiconductor switch opens after the capacitor is charged.

In an embodiment, the charge sub-branch comprises a resistor and aninductance connected in series with said capacitor for limiting thevalue and rate of variation of the charge current of said capacitor, inparticular within the operational limits of the first controlledsemiconductor switch.

In an embodiment, the resistance of said charge sub-branch resistor issuch that the charge current of said capacitor is within the operationallimits of the capacitor.

In an embodiment, the auxiliary branch comprises a discharge sub-branchconnected between the transmission line terminal and the commonterminal, said discharge sub-branch comprising a second controlledsemiconductor switch for closing the discharge sub-branch anddischarging the capacitor to the transmission line when the circuitbreaker is opened in operation, for suppressing the surge voltage acrossthe circuit breaker.

In an embodiment, the surge suppressor is arranged such that the secondcontrolled semiconductor switch opens after the capacitor is discharged.

In an embodiment, the discharge sub-branch comprises a resistor and aninductance connected in series with said capacitor for limiting thevalue and rate of variation of the discharge current of said capacitor,in particular within the operational limits of the second controlledsemiconductor switch.

In an embodiment, the capacitance of the capacitor and resistance of thedischarge sub-branch resistor are such that the stored energy by thepre-charged capacitor and by the cable inductance in operation isdissipated by said resistor without damage to the resistor or thecircuit breaker.

In an embodiment, the first controlled semiconductor is a thyristor.

In an embodiment, the surge suppressor is arranged such that the triggersignal from the gate of the first controlled semiconductor is removedafter the capacitor is charged.

In an embodiment, the first controlled semiconductor is a IGBT or IGCTor MOSFET or GTO.

In an embodiment, the second controlled semiconductor is a thyristor.

In an embodiment, the surge suppressor is arranged such that the triggersignal from the gate of the second controlled semiconductor is removedafter the capacitor is discharged.

In an embodiment, the second controlled semiconductor is a IGBT or IGCTor MOSFET or GTO.

It is also described a circuit breaker comprising the surge suppressoraccording to any the disclosed embodiments.

In an embodiment, the main breaker unit of the circuit breaker is asolid-state circuit breaker.

In an embodiment, the main breaker unit of the circuit breaker iscomprised of an association of IGBTs, IGCTs or power MOSFETs.

In an embodiment, the circuit breaker is for use in a point to point deconnection, meshed DC grid, multi-terminal HVDC grid, multi infeed HVDCgrid or point to point HVDC line.

It is also described a direct-current power transmission line with twoactive grids at both ends of the transmission line, comprising twocircuit breakers according to any the disclosed embodiments, eachcircuit breaker being arranged at one of the ends of the powertransmission line.

It is also described a direct-current power transmission line with oneactive grid at one end of the transmission line, comprising one circuitbreaker according to any of the disclosed embodiments, each circuitbreaker being arranged at the active grid end of the power transmissionline.

It is also described a direct-current power transmission grid comprisinga plurality of circuit breakers according to any the disclosedembodiments, each circuit breaker being arranged at one end of eachtransmission line of the power transmission grid.

A semiconductor switch may comprise one active semiconductor or anynumber of semiconductor switches connected in series and/or parallel tosupport the voltage and current rating of system.

The polarity of the DC bus, DC line and thus the direction of thesemiconductor switches can be reversed.

A transmission line can be based on any conducting technology includingany kind of overhead lines, DC or HVDC insulated or non-insulated cablesand superconducting DC or HVDC cables.

Depending on the application, the common terminal of the surgesuppressor branch can be connected to the ground or any other point ofthe DC system.

The same inductance can be shared by charge and discharge sub-branches.The charge sub-branch may comprise a resistor, an inductance or both aresistor and an inductance for current-limiting. The circuit breaker mayhave its line terminal connected through an additional inductance.

The surge suppression may be full or partial, for example if thecapacitor is not fully charged or the voltage of the charge is belownominal voltage.

The DC bus terminal is the terminal for connection to a DC source, DCload, DC converter, in particular a voltage source converter (VSC).

BRIEF DESCRIPTION OF THE DRAWINGS

The following figures provide preferred embodiments for illustrating thedescription and should not be seen as limiting the scope of invention.

FIG. 1: Schematic representation of bidirectional semiconductor valves.

FIG. 2(a): Schematic representation of simplified equivalent circuit ofa DC system.

FIG. 2(b): Schematic representation of typical SSCB structure with MOVin parallel.

FIG. 2(c): Schematic representation of typical SSCB structure with MOVin series with freewheeling diode.

FIG. 3(a): Schematic representation of a three terminal SSCB with thedisclosed surge suppressor branch for positive polarity.

FIG. 3(b): Schematic representation of a three terminal SSCB with thedisclosed surge suppressor branch for negative polarity.

FIG. 4: Schematic representation of HVDC transmission line equipped byan embodiment of the SSCB at the both ends.

FIG. 5(a): Schematic representation of the charging stage of anembodiment of the circuit breaker.

FIG. 5(b): Schematic representation of the current flow in normalcondition of an embodiment of the circuit breaker.

FIG. 6(a): Schematic representation of the initial interruption stage ofan embodiment of the circuit breaker.

FIG. 6(b): Schematic representation of the final interruption stage ofan embodiment of the circuit breaker.

FIG. 7: Schematic representation of the final interruption stagesimplified equivalent circuit for pole to pole short-circuit faultaccording to an embodiment of the circuit breaker.

FIG. 8: Schematic representation of cross-section of a 320 kV XLPEinsulated HVDC cable.

FIG. 9: Schematic representation of the system under study according toan embodiment of the circuit breaker.

FIG. 10: Schematic representation of converter currents: (a) rectifierpositive pole, (b) rectifier negative pole, (c) inverter positive pole,(d) inverter negative pole.

FIG. 11: Schematic representation of circuit breakers voltage at: (a)rectifier positive pole, (b) rectifier negative pole, (c) inverterpositive pole, (d) inverter negative pole.

FIG. 12: Schematic representation of the positive and negative cablescurrent around the interruption instant at: (a) rectifier side, (b)inverter side.

FIG. 13: Schematic representation of (a) charging stage of an embodimentof the circuit breaker; (b) initial interruption stage of an embodimentof the circuit breaker; (c) final interruption stage of an embodiment ofthe circuit breaker; wherein the main breaker unit of the fast DCcircuit breaker is comprised of an association of IGBTs.

DETAILED DESCRIPTION

Emerging DC grids applications demand fast short-circuit fault currentinterruption. Fast DC circuit breakers are identified as the feasiblesolution to handle the DC fault current. Switching overvoltage acrossthe DC circuit breakers is destructive for the interrupter device andalso for the other components of the system. The disclosed surgesuppressor branch can attach to any kind of fast DC interrupter devicesincluding the fast and ultra-fast hybrid DC circuit breakers and fastsolid-state circuit breakers. An auxiliary branch for limiting andsuppressing the excessive voltage across the fast DC circuit breaker forDC applications is discussed in this disclosure. Instead of conventionalapproaches, a pre-charged capacitor is used for soft switching. Toclarify the current interruption concept a fast solid-state circuitbreaker (SSCB) is equipped by the surge suppressor auxiliary branch anddifferent modes of operation of the fast DC circuit breaker are analysedand also design process of circuit parameters are described. Finally,main results are presented.

The topology of the disclosed surge suppressor branch in integrationwith a fast solid-state DC circuit breaker is discussed in this section.To have an application example of the disclosed surge suppressor device,its application in an HVDC link is illustrated, but other applicationsin DC power transmission are possible beyond HVDC.

The schematic of the disclosed surge suppressor branch attached to fastDC circuit breaker is depicted in FIG. 3(a) and FIG. 3(b). FIG. 3(a)shows the disclosed surge suppressor branch and arrangement of itscomponents for positive polarity of any DC system whereas the FIG. 3(b)illustrates the mentioned items for the negative polarity of the DCsystem.

FIG. 4 shows a point to point VSC-HVDC connection which is equipped bythe disclosed SSCB at the both ends of the transmission line. Fromtechnical point of view both of the circuit breakers are the same. TheSSCB has a main breaker unit which can be implemented by series andparallel connection of IGBTs or IGCTs or any other kind of fast gatecontrolled semiconductor switches. In addition to the main breaker unittwo thyristor banks are also employed. The thyristors of the disclosedsurge suppressor branch can be replaced by any type of gate controlledsemiconductor switches like IGBTS, IGCTs, GTOs and MOSFETs. Capacitor C₁and resistor R₂ play the main roles in fault current interruption andovervoltage limiting process. L₂ is employed to limit the rate of riseof fault current. Typically, HVDC transmission lines utilize currentsmoothing inductors which can be combined with the current limitinginductor of the circuit breaker. Combination of disclosed surgesuppressor branch to any kind of fast DC circuit breaker can remove theapplication of nonlinear surge arrestors like MOVs. MOVs could presentbeside the disclosed surge suppressor branch as a backup protectivedevice and not for energy absorbing purposes.

During normal operation condition the circuit breaker should be closedto maintain the power flow from the rectifier side to the inverter sideof the HVDC system. Considering VSC1 as the rectifier and VSC2 as theinverter side of depicted HVDC connection in FIG. 4, after turning onthe main breaker unit (controlled semiconductor switches) of SSCB1 andSSCB2 the current flows through the semiconductor switches of SSCB1 intothe DC transmission line and then via the semiconductor switches (e.g.anti-parallel diodes) of the SSCB2 into the inverter. Similar situationwill happen if the power flow direction changes. After detection of ashort-circuit fault and receiving the trip signal from the protectionsystem, the fault clearing process must be started.

At the initial state of the circuit breaker all the thyristors and thesemiconductor switches of the main breaker unit are in off state. As thefirst step of turn-on process, if the DC bus of the converter isenergized and has the rated voltage, C₁ should be charged up to thenominal voltage level. Charging of C₁ commences after triggering thegate of T₁. The equivalent circuit for the charging stage of thecapacitor is shown in the FIG. 5(a). The current flows through R₁ and L₁and charges C₁. Since capacitors have a limited charging current peak,R₁ is employed to control the maximum current while L₁ limits thederivative of charging current. Limiting the rate of rise of chargingcurrent is necessary because the thyristors also have specific di/dtcapabilities. T₁ naturally turns off after the charging current fallsbelow the holding current of the thyristor. If T₁ is not a thyristor andis an IGBT or IGCT or MOSFET it should turn off by removing the triggersignal from its gate. If the DC bus is not energized yet, like the DCbus of VSC2 in FIG. 4 which is the DC bus of the inverter side, then T₄will not be triggered. In fact, the charging stage the SSCB at theinverter side will only be done after the inverter DC bus reaches thesystem rated voltage.

The next step is to close the main breaker unit. Closing process of mainbreaker unit can be done by sending turn-on signal to the semiconductorswitches drivers. Depend on the voltage and current rating of system,main breaker unit may consist of a number of semiconductor switches inseries and parallel. Number of semiconductor switches in series can bedefined by the rated and surge voltage of system while the number ofparallel branches can be defined by maximum continuous and the surgecurrent of the system. The equivalent circuit of system in normaloperation mode is shown in FIG. 5(b).

After a pole to pole short-circuit or a pole to ground fault happens inthe HVDC transmission line, the fault detection relay detects the faultand sends the interruption command to the control system of the circuitbreaker. The fault current flows through the main breaker unit, untilthe trip signal is received. Thereafter, the main interruption processstarts. Concurrent with turning the main breaker unit off, T₂ must betriggered. This will connect the C₁ to the fault current path via L₁ andR₂ and will let the C₁ to feed the fault impedance while the mainbreaker unit is being turn off. In this surge suppressor branch R₂ canbe directly connected to the C₁. In this case after triggering the T₂the C₂ will be connected to the fault current via R₂ and L₁ will not bea part of this circuit. This alternative is depicted by dashed line inthe FIG. 5(a). The equivalent circuit for this phase of operation isshown in FIG. 6(a). After the main breaker unit completely turned off,C₁ continues feeding the fault impedance. The stored energy inpre-charged capacitor and also cable inductance will be naturallydissipated in R₂, cable resistance and fault impedance. The equivalentcircuit of final phase of interruption process is depicted in FIG. 6(b).

Assuming simple model of transmission line, it can be seen from FIG.6(b) that the final equivalent circuit is actually a series RLC circuit.Needless to say that T₂ will turn off naturally after the fault currentfalls below its holding current value. After interruption process iscompleted and C₁ is discharged, the circuit breaker is ready to startoperation again in normal conduction mode and repeat the fault currentinterruption process. If the inverter side of system is connected to agrid without generation units or only to loads, the SSCB2 can beeliminated since there is no need for current interruption at the loadside.

C1 charges up to the nominal voltage of system prior to operation ofcircuit breaker. The main advantage of having the capacitor pre-chargedis to provide the system with the capability of suppressing the surgevoltage across the circuit breaker during the interruption process ofthe DC fault current right after closing the breaker. This situation canhappen when a fault in the DC line happens before closing the circuitbreaker or a previously happened DC fault has not been removed yet.

Additionally, it is an advantage of the disclosure to use thyristors orother gate controlled switches in the surge suppressor branch. In caseof fault in DC bus of system which is behind the circuit breaker(between the circuit breaker and the VSC, i.e. the side opposite to thetransmission line), it is possible to prevent the capacitor fromdischarging and avoiding that the charged capacitor contributes to thefault situation. In this situation of a fault behind the circuitbreaker. It is a particular feature and advantage of the disclosure thata second circuit breaker, with a surge suppressor as disclosed, arrangedat the end of the transmission line, is in fact well equipped to breakthe circuit and suppress the surge because of the fault that occurredbehind the first circuit breaker.

In order to clarify the calculation method of parameters, designprocedure is explained in this section. Parameters of circuit breakershould be designed based on the power and voltage rating of system.IGBTs or IGCTs could be used in main breaker unit. To support thenominal voltage and current rating of the system, semiconductor switchesshould be connected in series and parallel. The number of IGBTs or IGCTsin series is given by (2).

$\begin{matrix}{N_{sw} = \frac{V_{D\; C}}{V_{{CE},{D\; C}}}} & (2)\end{matrix}$

where N_(sw), V_(DC) and V_(CE,DC) are the number of semiconductorswitches in series, nominal DC voltage of the system and permanent DCvoltage across the switch for 100 FIT failure rate, respectively. Thenumber of switches in parallel could also be calculated based on thepossible peak of fault current and the repetitive surge current of theIGBTs. Generally, for calculating the parameters of circuit breaker theworst cases should be considered. Approximated conduction loss of thecircuit breaker is given by following equation:

P _(loss) =N _(sw) ×V _(sat) ×I _(line)  (3)

where V_(sat) is the saturation voltage of switch in conduction mode andalso I_(line) is the nominal current of system. Despite the conventionalstructures which usually employ two IGBTs in their valve cells toguarantee the bidirectional current flow, the disclosed SSCB uses onlyone IGBT instead of two. In the other word, for the equal rated voltagelevels, the number of IGBTs in the disclosed SSCB is half of the numberof IGBTs in conventional approaches. Considering the current path in thedisclosed SSCB and the conventional ones, it is expected to havesignificantly reduced losses.

The value of L₁ should be calculated based on di/dt capability of T₁ andT₂ to protect them from destructive rate of rise of current. L₁ mustlimit the di/dt below than (di_(T)/dt)_(cr) which is critical currentderivative for the semiconductor switch. R₁ is responsible to limit thepeak of charging current of capacitor. So it can be calculatedconsidering the maximum peak current of C₁. L₂ is employed for limitingthe rate of rise of fault current particularly when the fault isoccurred very close to the circuit breaker. In this case, because ofabsence of the cable or overhead line inductance, fault current couldrapidly reach to destructive high values. The value of L₂ must becalculated considering the maximum allowable repetitive surge current ofpower semiconductor switches, fault detection threshold, the delay offault identification relay and system current smoothing reactors.Assuming repetitive surge current of switches as I_(CRM) and a safetyfactor of 1.5 and T_(Delay) as the fault identification circuit delayand also I_(th) as the threshold level for overcurrent protectionfollowing expressions can be developed:

$\begin{matrix}{I_{{ma}\; x} = \frac{I_{CRM}}{1.5}} & (4) \\{{\Delta \; I} = {I_{{ma}\; x} - I_{th}}} & (5) \\{L_{2} = {\frac{V_{D\; C} \times T_{delay}}{\Delta \; I} - L_{smoothing}}} & (6)\end{matrix}$

The main parameters of the circuit breaker are the C₁ and R₂. Theequivalent circuit depicted in FIG. 6(c) represents a series RLCcircuit. The differential equation for this circuit is given by (7).

$\begin{matrix}{{\frac{d^{2}{i(t)}}{{dt}^{2}} + {\frac{\left( {R_{2} + R_{fault} + R_{cable}} \right)}{\left( {L_{1} + L_{2} + L_{cable}} \right)}\frac{{di}(t)}{dt}} + {\frac{1}{\left( {L_{1} + L_{2} + L_{cable}} \right) \cdot C_{1}}{i(t)}}} = 0} & (7)\end{matrix}$

The damping factor of equivalent RLC circuit can be given by (8).

$\begin{matrix}{\xi = {\frac{\left( {R_{2} + R_{fault} + R_{cable}} \right)}{2}\sqrt{\frac{C_{1}}{\left( {L_{1} + L_{2} + L_{cable}} \right)}}}} & (8)\end{matrix}$

When ξ>1 the circuit has an over-damped response while for ξ<1 theresponse is under-damped. For proper operation of the circuit breakerthe worst scenario should be taken into account and the parameters ofequivalent circuit should be calculated for the over-damped response.

The value of R₂ should be calculated based on the maximum possible valueof fault current at the interruption instant which is the I_(max). It isalso necessary to consider a safety factor (k) for practicalimplementation purposes. k can lie in the range of 1.1 to 1.5. Hence R₂can be given by:

$\begin{matrix}{R_{2} = \frac{V_{C_{1}}}{k \cdot I_{{ma}\; x}}} & (9)\end{matrix}$

After defining the value of R₂ it is possible to calculate the value ofC₁. The worst case for calculating the value of C₁ is to have ashort-circuit fault at the end of the transmission line. In this case, alarge amount of energy is stored in the transmission line. So forcalculation of C₁ the total value of cable inductance must beconsidered. Moreover, the fault impedance and the cable resistanceshould be neglected to consider the worst case. Therefore, assuming ξ>1the value of C₁ is obtainable with the following equation:

$\begin{matrix}{C_{1} > \frac{4 \times \left( {L_{1} + L_{2} + L_{cable}} \right)}{\left( R_{2} \right)^{2}}} & (10)\end{matrix}$

The design of the circuit breaker based on the pole to ground fault canalso cover the pole to pole faults. In fact, pole to pole faults canhappen in symmetric monopole and the bipolar HVDC systems. Since thereare two SSCBs which are installed at the both ends of the transmissionlines, and also system has two transmission lines hence four SSCBs worktogether to protect the system. In case of a pole to pole short-circuitfault the inductance of system including the smoothing reactors,limiting inductors of SSCBs and the transmission line resistance andalso limiting resistance of SSCBs are doubled. If the new values are putin equation (10) the capacitor value will be obtained equal to half ofcalculated value for the studied pole to ground case. But, in fact,since two SSCBs from each pole of converter interrupt the fault currentso two capacitors will be in series connection with each other and thiswill reduce their total capacity to the half of each one. Therefore thecalculated value is still valid for the pole to pole fault. Thesimplified equivalent circuit of a symmetric monopole system under poleto pole fault at the final stage of the interruption is shown in FIG. 7.

Parameters of circuit breaker are designed based on assumed ratings of asymmetric monopole HVDC system which are presented in Table. I. Toachieve more accurate results, the simulation study is carried out inelectromagnetic transient type software namely PSCAD. HVDC cable ismodelled by frequency dependent cable model with inserting the physicalfeatures of the cable in PSCAD. The physical dimensions of the cableobtained from [18]. FIG. 8 depicts the cross section of the HVDC cable.

Since the modern HVDC systems relies on modular multilevel converters(MMC), the simulation study is performed on MMC based HVDC system. TheMMCs are modelled as average models. FIG. 9 shows the schematic ofstudied system. Table. II shows the parameters of designed SSCB.

To perform the study and analyse the results a pole to poleshort-circuit fault is supposed to happen at t=2s. In this study it issupposed to install the SSCB between the converter and the smoothingreactor. The IGBTs of the MMCs are also blocked after detection of ashort-circuit fault. Additionally, the short-circuit fault is analysedat 3 different points. As it can be seen from FIG. 9, point A is veryclose to the rectifier while point B is 90 km far from the rectifier andit is very close to the inverter. Point C has 45 km distance from bothof the converters. To validate the functionality of the SSCB a thresholdbased protection scheme is modelled. When the fault current reaches thethreshold level of protection system the interruption process starts. Toconsider the practical implementation limitations, the delay of currentsensors and also fault identification relay is supposed to be 500 μs.

TABLE I Assumed system parameters MMC Power 1000 MVA Cable Length 90 kmTransformer Y/D Nominal Voltage ±320 kV Smoothing Reactor 15 mH ACsource 230 kV Configuration Sym. monopole Fault Impedance 0.1Ω MMC TypeHalf-bridge

TABLE II Designed SSCB parameters I_(th) 3 kA R₁ 3 kΩ L₁ 50 μH C₁ 350 μFR₂ 30Ω L₂ 10 mH

FIG. 10(a) depicts the I¹ _(p) which is the current of the positive poleof the MMC1 for different fault locations. When the fault is at thepoint A which is very close to the rectifier the fault current risessharply. The main reason for the high rate of rise of current is theabsence of transmission line inductance. On the other hand, for thefaults with far distance from the rectifier like the fault at the pointB, the fault current starts rising with a delay. It is clear that thecable inductance resists against the change of current. I¹ _(n) which isthe current of the negative pole of the MMC1 is also shown in FIG.10(b). The same explanation is also valid for the negative pole currentduring the short-circuit fault. At the inverter side of the system, thecurrent (I² _(p)) has a negative value in the positive pole. When ashort-circuit fault happens in the transmission line, the direction ofcurrent reverses and increases until reaches the protection threshold.The current reversal is because of the anti-parallel diodes of IGBTs. Infact, even after blocking the IGBTs, the MMC is still defencelessagainst the pole to pole short-circuit and it feeds the fault current.The situation is similar for the negative pole of the inverter. FIG.10(c) shows the inverter positive pole current for different faultlocations. I², which represents the inverter negative pole current isdepicted in FIG. 10(d).

All the waveforms present an ultra-fast interruption of the faultcurrent and cutting it from the related converter. The interruption timeis less than 300 μs. The ultra-fast operation of the circuit breakerprevents the fault current from reaching very high values. Consequently,interrupting the current at lower values leads to smaller footprint ofthe circuit breaker.

In addition to the ultra-fast operation of the disclosed solid-statecircuit breaker, having limited transient surge voltage is also one ofits significant features. Despite the conventional topologies for thesolid-state circuit breakers which utilize the nonlinear surge arrestorsto absorb the stored energy and also clamp the overvoltage, thedisclosed topology uses a concept in cutting the converter currentsafely and discharging the cable energy naturally. FIG. 11 illustratesthe circuit breakers voltage around the interruption instant for the 3different fault locations.

It can be seen in FIG. 11(a) that not only is the transient overvoltagelimited to less than 370 kV but also has only 2 ms time duration whichlies in the safe operation area of all the power electronic componentsof the system with a large safety margin. When the fault is very closeto the circuit breaker like the fault at point A, the overvoltage islower than the other cases. FIG. 11(b) shows the circuit breaker voltagefor the negative pole of the rectifier. It can also be seen that theovervoltage is limited to less than 380 kV. The inverter positive polecircuit breaker voltage is depicted in FIG. 11(c). The surge voltage islimited to less than 350 kV. As it is shown in FIG. 11(d) the transientsurge voltage of the circuit breaker for the negative pole of theinverter is also limited to less than 380 kV. Therefore, it can beobserved that the surge voltage is limited to almost 18% of the ratedvoltage without use of the surge arrestors. Surge arrestors can beattached to the disclosed topology, advantageously only as commonprotective devices. Since the surge arrestor is not used for the energyabsorption purpose in this topology, it has smaller size and footprintthan the conventional design.

As it was mentioned in previous sections, the disclosed DC circuitbreaker interrupts the fault current from the converter by connecting alimited voltage source (capacitor) to the cable to allow the faultcurrent to continue until dissipates naturally in a formed equivalentRLC circuit. The next phase of functionality of the circuit breaker isnot related to the interruption process because not only can the faultcurrent be interrupted from the converter before this stage but alsoeven can be isolated from the converter and also the rest of system.This phase of operation includes the isolated faulty cables dischargeprocess.

FIG. 12(a) illustrates the positive and negative cables current at therectifier side while the FIG. 12(b) shows the cables current at theinverter side. As it is expected the cable current reaches 8 kA which ishigher than the peak value for the converter current. This is because ofpresence of capacitor after turning off the IGBTs of the circuitbreaker. The discharge time can be designed to be faster or slower basedon the circuit breaker parameters. There should be a trade-off betweenthe circuit breaker size, peak current, surge voltage level and alsodischarge time.

In conclusion, the interruption of high DC fault currents in very shortperiod of time can generate highly destructive excessive voltage acrossthe breaking device which is also harmful for the other components ofthe system. A fast solid-state HVDC circuit breaker which is equipped bythe surge suppressor branch is disclosed and the results analysed.Obtained results confirm that the disclosed auxiliary surge suppressorapparatus is able to limit the transient surge voltage within theacceptable range. The combination of the disclosed surge suppressorbranch with the fast solid-state current interrupter devices cut thefault current from the related converter, before it reaches high values.This feature also reduces the sizing of semiconductor devices inside theSSCB.

Moreover, the disclosed SSCB employs less number of IGBTs and diodes incomparison with the conventional structures and has less power losses.Total power losses of the circuit breaker with IGBT based main breakerunit is less than 0.08% of rated power which is quite less than powerlosses of related VSC. The conduction power losses of the circuitbreaker could fall below 0.04% of rated power if main breaker unit isimplemented with IGCTs.

In addition, the disclosed circuit breaker uses simple components likecapacitor and resistors for discharging the stored energy of the cableinstead of MOVs which makes it more economical and robust and eliminatesneed for regular maintenance. All in all, results show significantimprovements in comparison with prior-art circuit breaker topologies.

The disclosure should not be seen in any way restricted to theembodiments described and a person with ordinary skill in the art willforesee many possibilities to modifications thereof.

The above described embodiments are combinable.

The following claims further set out particular embodiments of thedisclosure.

1. A surge suppressor for a direct-current power transmission circuitbreaker having a DC bus terminal, a transmission line terminal, and acommon terminal, said suppressor comprising, an auxiliary branchcomprising a pre-chargeable capacitor, wherein the auxiliary branch isarranged such that: the capacitor is configured to be charged by the DCbus before the circuit breaker is closed for operation; and thecapacitor is connected to be discharged to the transmission line whenthe circuit breaker is opened in operation, for suppressing the surgevoltage across the circuit breaker.
 2. The surge suppressor of claim 1,wherein the auxiliary branch comprises a charge sub-branch connectedbetween the DC bus terminal and the common terminal, said chargesub-branch comprising a first controlled semiconductor switch forclosing the charge sub-branch and charging the capacitor by the DC busbefore the circuit breaker is closed.
 3. The surge suppressor of claim2, wherein the surge suppressor is arranged such that the firstcontrolled semiconductor switch opens after the capacitor is charged. 4.The surge suppressor of claim 2, wherein the charge sub-branch comprisesa resistor and an inductance connected in series with said capacitor forlimiting a value and rate of variation of a charge current of saidcapacitor, in particular within operational limits of the firstcontrolled semiconductor switch.
 5. The surge suppressor of claim 4,wherein a resistance of said charge sub-branch resistor is such that thecharge current of said capacitor is within the operational limits of thecapacitor.
 6. The surge suppressor of claim 1, wherein the auxiliarybranch comprises a discharge sub-branch connected between thetransmission line terminal and the common terminal, said dischargesub-branch comprising a second controlled semiconductor switch forclosing the discharge sub-branch and discharging the capacitor to thetransmission line when the circuit breaker is opened in operation, forsuppressing the surge voltage across the circuit breaker.
 7. The surgesuppressor of claim 6, wherein the surge suppressor is arranged suchthat the second controlled semiconductor switch opens after thecapacitor is discharged.
 8. The surge suppressor of claim 6, wherein thedischarge sub-branch comprises a resistor and an inductance connected inseries with said capacitor for limiting a value and rate of variation ofa discharge current of said capacitor, in particular within operationallimits of the second controlled semiconductor switch.
 9. The surgesuppressor of claim 8, wherein a capacitance of the capacitor andresistance of the discharge sub-branch resistor are such that the energystored by the pre-charged capacitor and by the cable inductance inoperation is dissipated by said resistor without damage to the resistoror the circuit breaker.
 10. The surge suppressor of claim 1, wherein thefirst controlled semiconductor is a thyristor.
 11. The surge suppressorof claim 1, wherein the first controlled semiconductor is an IGBT orIGCT or MOSFET or GTO.
 12. The surge suppressor of claim 1, wherein thesecond controlled semiconductor is a thyristor.
 13. The surge suppressorof claim 1, wherein the second controlled semiconductor is an IGBT orIGCT or MOSFET or GTO.
 14. A direct-current power transmission circuitbreaker comprising: a surge suppressor for the direct-current powertransmission circuit breaker having a DC bus terminal, a transmissionline terminal, and a common terminal, said suppressor comprising: anauxiliary branch comprising a pre-chargeable capacitor, wherein theauxiliary branch is arranged such that: the capacitor is configured tobe charged by the DC bus before the circuit breaker is closed foroperation; and the capacitor is connected to be discharged to thetransmission line when the circuit breaker is opened in operation, forsuppressing the surge voltage across the circuit breaker.
 15. Thedirect-current power transmission circuit breaker of claim 14, furthercomprising: a main breaker unit, wherein the main breaker unit of thecircuit breaker is a solid-state circuit breaker.
 16. The direct-currentpower transmission circuit breaker of claim 15, wherein the main breakerunit of the circuit breaker is comprised of an association of IGBTs,IGCTs or power MOSFETs.
 17. The direct-current power transmissioncircuit breaker of claim 14, wherein the breaker is configured for usein a point to point DC connection, meshed DC grid, multi-terminal HVDCgrid, multi infeed HVDC grid or point to point HVDC line.
 18. (canceled)19. A direct-current power transmission line having two ends forconnection to one active grid at one end of the transmission line,comprising: a circuit breaker being arranged at the active grid end ofthe power transmission line, the circuit breaker comprising: a surgesuppressor for the circuit breaker having a DC bus terminal, atransmission line terminal, and a common terminal, said suppressorcomprising: an auxiliary branch comprising a pre-chargeable capacitor,wherein the auxiliary branch is arranged such that: the capacitor isconfigured to be charged by the DC bus before the circuit breaker isclosed for operation; and the capacitor is connected to be discharged tothe transmission line when the circuit breaker is opened in operation,for suppressing the surge voltage across the circuit breaker. 20.(canceled)
 21. A direct-current power transmission line for two activegrids, each grid at each end of the line, comprising two circuitbreakers according to claim 14, each circuit breaker being arranged atone of the ends of the power transmission line.
 22. A direct-currentpower transmission circuit breaker of claim 14, wherein the circuitbreaker is configured for use in a direct-current power transmissiongrid, the circuit breaker being arranged at one end of a transmissionline of the power transmission grid.